Renesas Electronics /R7FA6M4AF /SCI0 /SCR

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Interpret as SCR

7 43 0 0 00 0 0 0 0 0 0 0 0 (Others)CKE0 (0)TEIE 0 (0)MPIE 0 (0)RE 0 (0)TE 0 (0)RIE 0 (0)TIE

TEIE=0, RIE=0, TE=0, CKE=Others, TIE=0, MPIE=0, RE=0

Description

Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)

Fields

CKE

Clock Enable

0 (00): In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin.

0 (Others): In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. The SCKn pin is available for use as an I/O port based on the I/O port settings when the GPT clock is used. In clock synchronous mode, the SCKn pin functions as the clock input pin.

1 (01): In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin.

TEIE

Transmit End Interrupt Enable

0 (0): Disable SCIn_TEI interrupt requests

1 (1): Enable SCIn_TEI interrupt requests

MPIE

Multi-Processor Interrupt Enable

0 (0): Normal reception

1 (1): When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed.

RE

Receive Enable

0 (0): Disable serial reception

1 (1): Enable serial reception

TE

Transmit Enable

0 (0): Disable serial transmission

1 (1): Enable serial transmission

RIE

Receive Interrupt Enable

0 (0): Disable SCIn_RXI and SCIn_ERI interrupt requests

1 (1): Enable SCIn_RXI and SCIn_ERI interrupt requests

TIE

Transmit Interrupt Enable

0 (0): Disable SCIn_TXI interrupt requests

1 (1): Enable SCIn_TXI interrupt requests

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